MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 519

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
Reserved
Reserved
Reserved
LCKON
PRECS
PLLIE1
PLLIE0
PLLPD
LOCIE
15–14
13–12
10–8
Field
6–5
11
7
4
3
2
PLL Interrupt Enable 1
An optional interrupt can be generated when the PLL lock status bit (LCK1) in the OCCS Status Register
(STAT) changes.
00
01
10
11
PLL Interrupt Enable 0
An optional interrupt can be generated if the PLL lock status bit (LCK0) in the OCCS Status Register
(STAT) changes.
00
01
10
11
Loss of Reference Clock Interrupt Enable
The loss of reference clock circuit monitors the output of the on-chip oscillator circuit. In the event of loss
of reference clock, an optional interrupt can be generated.
An optional interrupt can be generated if the oscillator circuit output clock is lost.
0
1
This read-only bitfield is reserved and always has the value zero.
Lock Detector On
0
1
This read-only bitfield is reserved and always has the value zero.
PLL Power Down
The PLL can be turned off by setting the PLLPD bit. There is a four IPbus clock delay from changing the
bit to signaling the PLL. When the PLL is powered down, the gear shifting logic automatically switches to
ZSRC[1:0] = 01b in order to prevent loss of reference clock to the core.
0
1
This read-only bit is reserved and always has the value zero.
Prescaler Clock Select
This bit is used to select between (the external clock source or oscillator) and the internal relaxation
oscillator.
NOTE: This bit should not be set unless the external reference is enabled in the GPIO/SIM/KTR.
Interrupt disabled
Interrupt enabled
Lock detector disabled
Lock detector enabled
PLL enabled
PLL powered down
Disable interrupt
Enable interrupt on any rising edge of LCK1
Enable interrupt on falling edge of LCK1
Enable interrupt on any edge change of LCK1
Disable interrupt
Enable interrupt on any rising edge of LCK0
Enable interrupt on falling edge of LCK0
Enable interrupt on any edge change of LCK0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
OCCS_CTRL field descriptions
Table continues on the next page...
Preliminary
Description
Chapter 15 On-Chip Clock Synthesis (OCCS)
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