MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 401

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

12.4.1.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit is clear. In slave mode the SCLK
pin is the input for the serial clock from the master DSC. Before a data transaction
occurs, the SS pin of the slave SPI must be at logic zero. SS must remain low until the
transaction completes or a mode fault error occurs.
In a slave SPI module, data enters the shift register under the control of the serial clock,
SCLK, from the master SPI module. After a full data word enters the shift register of a
slave SPI, it transfers to the receive data register, DRCV, and the SPRF bit is set. To
prevent an overflow condition, slave software then must read the receive data register
before another full data word enters the shift register.
The maximum frequency of the SCLK for an SPI configured as a slave is less than 1/2
the bus clock frequency. The frequency of the SCLK for an SPI configured as a slave
does not have to correspond to any SPI baud rate as defined by the SPR bits. The SPR
bits control only the speed of the SCLK generated by an SPI configured as a master.
When the master SPI starts a transaction, the data in the slave shift register begins
shifting out on the MISO pin. The slave can load its shift register with new data for the
next transaction by writing to its transmit data register. The slave must write to its
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The SPI must be enabled (SPE = 1) for slave transactions to be
received.
Data in the transmitter shift register is unaffected by SCLK
transitions when the SPI operates as a slave but is deselected
(SS = 1).
Figure 12-8. Full-Duplex Master-Slave Connections
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Preliminary
Note
Note
Chapter 12 Queued Serial Peripheral Interface (QSPI)
401