MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 402

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Operating Modes
transmit data register at least one bus cycle before the master starts the next transaction.
Otherwise, the data that was last transmitted is reloaded into the slave shift register and
shifts out on the MISO pin again. Data written to the slave shift register during a
transaction remains in a buffer until the end of the transaction.
When the clock phase bit (CPHA) is set, the first edge of SCLK starts a transaction.
When CPHA is clear, the falling edge of SS starts a transaction.
12.4.1.3 Wired-OR Mode
Wired-OR functionality is provided to permit the connection of multiple SPIs. Figure
11-7 illustrates the sharing of a single master device between multiple slave SPIs. When
the WOM bit is set, the outputs switch from conventional complementary CMOS output
to open drain outputs.
12.4.2 Transaction Formats
During an SPI transaction, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock synchronizes shifting and sampling on the
two serial data lines. A slave select line allows selection of an individual slave SPI
402
GPIO Pins
SCLK must be in the proper idle state before the slave is
enabled to preserve the proper SCLK, MISO, MOSI timing
relationships.
Master
Device
M IS O
M O S I
S C L K
S S
S S 1
S S 2
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Figure 12-9. Master With Two Slaves
V
DD
Preliminary
Note
M IS O
M O S I
S C L K
M IS O
M O S I
S C L K
S S
S S
Device 2
Device 1
Slave
Slave
Freescale Semiconductor