MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 310

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
Addresses: GPIOA_PER – F140h base + 3h offset = F143h
9.2.5 GPIO Interrupt Assert Register (GPIOx_IAR)
This read and write register is only for software testing, but it also provides a software
interrupt capability. When the bit is set to one, an interrupt is asserted. The interrupt is
generated continually until this bit is cleared. Clear the bits in the register by writing
zeros.
Addresses: GPIOA_IAR – F140h base + 4h offset = F144h
310
Reset
Reset
Read
Read
Write
Write
Bit
Bit
15–0
15–0
Field
Field
PE
IA
15
15
0
0
GPIOB_PER – F150h base + 3h offset = F153h
GPIOC_PER – F160h base + 3h offset = F163h
GPIOD_PER – F170h base + 3h offset = F173h
GPIOE_PER – F180h base + 3h offset = F183h
GPIOF_PER – F190h base + 3h offset = F193h
GPIOB_IAR – F150h base + 4h offset = F154h
GPIOC_IAR – F160h base + 4h offset = F164h
GPIOD_IAR – F170h base + 4h offset = F174h
GPIOE_IAR – F180h base + 4h offset = F184h
GPIOF_IAR – F190h base + 4h offset = F194h
14
14
0
0
Peripheral Enable Bits
0
1
Interrupt Assert Bits
Pin is for GPIO (GPIO mode)
Pin is for peripheral (peripheral mode)
13
13
0
0
12
12
0
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
11
0
0
GPIOx_PER field descriptions
GPIOx_IAR field descriptions
10
10
0
0
0
0
9
9
Preliminary
0
0
8
8
PE
IA
Description
Description
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
0
0
3
3
Freescale Semiconductor
0
0
2
2
0
0
1
1
0
0
0
0