MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 601

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Address: HFM_CR – F400h base + 1h offset = F401h
Freescale Semiconductor
Reset
Read
Write
Bit
Reserved
Reserved
Reserved
KEYACC
CBEIE
15–11
LOCK
AEIE
CCIE
Field
4–2
10
9
8
7
6
5
15
0
14
0
This read-only bitfield is reserved and always has the value zero.
Write Lock Control
This bit is always readable. It may be set only once. When it is set, it cannot be cleared except by reset.
This bit provides additional security for the flash array by disabling writes to the protection register.
NOTE: When other bits in this register are written, this bit might also be written accidentally. Be careful
0
1
This read-only bit is reserved and always has the value zero.
Access Error Interrupt Enable
This bit enables an interrupt when an ACCERR flag is set.
0
1
Command Buffer Empty Interrupt Enable
This bit enables an interrupt when there is an empty command buffer in the flash memory.
0
1
Command Complete Interrupt Enable
This bit enables an interrupt when all commands are complete in the Flash.
0
1
Enable Security Key Writing
This bit is always readable. However, it can be written only if the KEYEN bit in the SECH register is set.
0
1
This read-only bitfield is reserved and always has the value zero.
The PROT register is writable.
The PROT register is write-locked.
ACCERR interrupts disabled.
An interrupt is requested when the ACCERR flag is set.
Command Buffer Empty interrupts disabled.
An interrupt is requested when the CBEIF flag is set.
Command Complete Interrupts Disabled.
An interrupt is requested when the CCIF flag is set.
Flash writes are interpreted as the start of a program or erase sequence.
Writes to Flash array are interpreted as keys to open the back door.
13
0
0
not to set this bit accidentally when modifying other bits.
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
0
HFM_CR field descriptions
Table continues on the next page...
10
0
0
0
9
Preliminary
AEIE
0
8
Description
0
7
CCIE
0
6
0
5
Chapter 20 Flash Memory (HFM)
0
4
0
0
3
0
2
LBTS
0
1
BTS
0
0
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