MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 80

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Functional Description
The conversion process is initiated either by a SYNC signal from one of the on-device
timer channels or by writing a 1 to a START bit.
Starting a single conversion actually begins a sequence of conversions, or a scan. The
ADC operates in either sequential scan mode or parallel scan mode. In sequential scan
mode, scan sequence is determined by defining sixteen sample slots that are processed in
order, SAMPLE[0:15]. In parallel scan mode, converter A processes SAMPLE[0:3] and
SAMPLE[8:11] in order, and converter B processes SAMPLE[4:7] and SAMPLE[12:15]
in order. SAMPLE slots can be disabled using the ADC_SDIS control register to
terminate a scan early.
In sequential scan mode, a scan takes up to sixteen single-ended or differential samples,
one at a time. See the following figure.
In parallel scan mode, eight of the sixteen samples are allocated to converter A and eight
are allocated to converter B. Two converters operate in parallel, and each can take at
most eight samples. Converter A can sample only analog inputs ANA[0:7], and converter
B can sample only analog inputs ANB[0:7].
80
ANB0
ANB2
ANB3
ANB4
ANB5
ANB6
ANB7
ANA0
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
ANB1
ANA1
SAMPLEn[3:0]
SAMPLEn[3:0]
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
Figure 2-67. ADC Sequential Scan Mode
Preliminary
A/D 0
A/D 1
Freescale Semiconductor
ADRSLT10
ADRSLT11
ADRSLT12
ADRSLT13
ADRSLT14
ADRSLT15
ADRSLT0
ADRSLT1
ADRSLT2
ADRSLT3
ADRSLT4
ADRSLT5
ADRSLT6
ADRSLT7
ADRSLT8
ADRSLT9