MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 448

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Register Definition
13.3.20 MSCAN Identifier Mask Registers (Second Bank)
The identifier mask register specifies which of the corresponding bits in the identifier
acceptance register are relevant for acceptance filtering. To receive standard identifiers in
32 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask
registers CAN_IDMR1 and CAN_IDMR5 to “don’t care.” To receive standard identifiers
in 16 bit filter mode, it is required to program the last three bits (AM[2:0]) in the mask
registers CAN_IDMR1, CAN_IDMR3, CAN_IDMR5, and CAN_IDMR7 to “don’t
care.”
These registers can be read anytime and can be modified by writing anytime in
initialization mode (INITRQ=1 and INITAK=1).
Addresses: CAN_IDMR4 – F440h base + 1Ch offset = F45Ch
13.3.21 MSCAN Receive and Transmit Buffer Identifier Register 0 -
The identifier registers for an extended format identifier consists of a total of 32 bits: the
ID[28:0], SRR, IDE, and RTR bits.
448
Reset
Read
Write
Bit
Reserved
15–8
Field
7–0
AM
15
0
CAN_IDMR5 – F440h base + 1Dh offset = F45Dh
CAN_IDMR6 – F440h base + 1Eh offset = F45Eh
CAN_IDMR7 – F440h base + 1Fh offset = F45Fh
(CAN_IDMRn)
Extended Identifer Mapping (CAN_nXFG_IDR0 (Extended))
14
0
This read-only bitfield is reserved and always has the value zero.
Acceptance Mask Bits
AM[7:0] If a particular bit in this register is cleared, this indicates that the corresponding bit in the identifier
acceptance register must be the same as its identifier bit before a match is detected. The message is
accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the
identifier acceptance register does not affect whether or not the message is accepted.
0
1
Match corresponding acceptance code register and identifier bits
Ignore corresponding acceptance code register bit
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
0
11
0
CAN_IDMRn field descriptions
10
0
0
9
Preliminary
0
8
Description
0
7
0
6
0
5
0
4
AM
0
3
Freescale Semiconductor
0
2
0
1
0
0