MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 236

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
7.3.36 PWM SM3 Interrupt Enable Register (PWM_SM3INTEN)
Address: PWM_SM3INTEN – F300h base + A3h offset = F3A3h
236
Reset
Read
Write
Bit
Reserved
CA1IE
CA0IE
CB1IE
CB0IE
15–14
REIE
Field
RIE
13
12
11
10
9
8
15
0
0
14
0
This read-only bitfield is reserved and always has the value zero.
Reload Error Interrupt Enable
This read/write bit enables the reload error flag, STS[REF], to generate CPU interrupt requests. Reset
clears this bit.
0
1
Reload Interrupt Enable
This read/write bit enables the reload flag, STS[RF], to generate CPU interrupt requests. Reset clears this
bit.
0
1
Capture A 1 Interrupt Enable
This bit allows the STS[CFA1] flag to create an interrupt request to the CPU.
0
1
Capture A 0 Interrupt Enable
This bit allows the STS[CFA0] flag to create an interrupt request to the CPU.
0
1
Capture B 1 Interrupt Enable
This bit allows the STS[CFB1] flag to create an interrupt request to the CPU.
0
1
Capture B 0 Interrupt Enable
This bit allows the STS[CFB0] flag to create an interrupt request to the CPU.
REIE
STS[REF] CPU interrupt requests disabled
STS[REF] CPU interrupt requests enabled
STS[RF] CPU interrupt requests disabled
STS[RF] CPU interrupt requests enabled
Interrupt request disabled for STS[CFA1].
Interrupt request enabled for STS[CFA1].
Interrupt request disabled for STS[CFA0].
Interrupt request enabled for STS[CFA0].
Interrupt request disabled for STS[CFB1].
Interrupt request enabled for STS[CFB1].
13
0
RIE
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
PWM_SM3INTEN field descriptions
CA1I
11
E
0
Table continues on the next page...
CA0I
10
E
0
0
9
Preliminary
0
8
Description
CX1I
E
0
7
CX0I
E
0
6
0
5
0
4
0
3
CMPIE
Freescale Semiconductor
0
2
0
1
0
0