MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 326

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Memory Map and Registers
10.3.4 I2C Status Register (I2Cx_SR)
Addresses: I2C0_SR – F210h base + 3h offset = F213h
326
Reset
Read
Write
Bit
Reserved
Reserved
WUEN
TXAK
RSTA
15–8
Field
Field
TCF
3
2
1
0
7
15
0
I2C1_SR – F220h base + 3h offset = F223h
14
0
0
1
Transmit acknowledge enable
Specifies the value driven onto the SDA during data acknowledge cycles for both master and slave
receivers. The value of the FACK bit affects NACK/ACK generation.
0
1
Repeat START
Writing a one to this bit generates a repeated START condition provided it is the current master. This bit
will always be read as zero. Attempting a repeat at the wrong time results in loss of arbitration.
Wakeup enable
I2C module can wake the core from stop mode when slave address matching occurs.
0
1
This read-only bit is reserved and always has the value zero.
This read-only bitfield is reserved and always has the value zero.
Transfer complete flag
This bit sets on the completion of a byte and acknowledge bit transfer. This bit is only valid during or
immediately following a transfer to or from the I2C module. The TCF bit is cleared by reading the I2C data
register in receive mode or by writing to the I2C data register in transmit mode.
Receive
Transmit
An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is
set) receiving byte.
No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is
set) receiving data byte.NOTE:SCL is held low until TXAK is written.
Normal operation. No interrupt generated when address matching in stop mode.
Enables the wakeup function in stop mode.
13
0
12
0
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
I2Cx_CR1 field descriptions (continued)
0
11
0
I2Cx_SR field descriptions
Table continues on the next page...
10
0
0
9
Preliminary
0
8
Description
Description
TCF
1
7
IAAS
0
6
BUSY
0
5
ARBL
0
4
0
0
3
Freescale Semiconductor
SRW
0
2
IICIF
0
1
RXAK
0
0