MC56F8257MLH Freescale Semiconductor, MC56F8257MLH Datasheet - Page 583

• Manufacturer Part Number: MC56F8257MLH
• Description: DSC 64K FLASH 60MHZ 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8257MLH

• Core Processor: 56800E
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x12b, D/A 1x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• Product: DSCs
• Processor Series: 56800E
• Core: 56800E
• Device Million Instructions Per Second: 60 MIPs
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 54
• Data Ram Size: 8 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Address: COP_TOUT – F110h base + 1h offset = F111h
18.2.3 COP Counter Register (COP_CNTR)
Address: COP_CNTR – F110h base + 2h offset = F112h
18.3 Functional Description
When the COP is enabled, each positive edge of the prescaled clock (COSC, ROSC, or IP
Bus clock) causes the counter to decrement by one. If the count reaches a value of
0x0000, then the device is reset. For the DSC core to show that it is operating properly, it
must perform a service routine before the count reaches 0x0000. The service routine
consists of writing 0x5555 followed by 0xAAAA to the CNTR register.
Freescale Semiconductor
Reset
Reset
Read
Read
Write
Write
Bit
TIMEOUT
Bit
SERVICE
COUNT_
15–0
15–0
Field
Field
15
15
1
1
14
14
1
1
COP Timeout Period
The value in this register determines the timeout period of the COP counter.
Restriction: These bits can be changed only when CWP is set to zero.
COP Count/Service
COP Count: When this register is read, its value is the current value of the COP counter as it counts down
from the timeout value to zero. A reset is issued when this count reaches zero.
COP Service: Write to this register to service the counter. When enabled, the COP requires that a service
sequence be performed periodically to clear the COP counter and prevent a reset from being issued.
• This routine consists of writing 0x5555 to CNTR followed by writing 0xAAAA before the timeout
• These writes to CNTR must be performed in the correct order, but any number of other instructions
13
13
1
1
period expires.
(and writes to other registers) may be executed between the two writes.
12
12
1
1
MC56F825x/4x Reference Manual, Rev. 2, 10/2010
11
11
1
1
COP_TOUT field descriptions
COP_CNTR field descriptions
10
10
1
1
1
1
9
9
Preliminary
COUNT_SERVICE
TIMEOUT
1
1
8
8
Description
Description
1
1
7
7
Chapter 18 Computer Operating Properly (COP)
1
1
6
6
1
1
5
5
1
1
4
4
1
1
3
3
1
1
2
2
1
1
1
1
1
1
0
0
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