R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 957

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• The command response is received from the card.
• The end of the command sequence is detected by poling the BUSY flag in CSTR or by the
• Check whether the state is data busy through the DTBUSY bit in CSTR. If data busy is
• Write the CMDOFF bit to 1, if a CRC error (CRCERI) or a command timeout error (CTERI)
• The MCCMD and MCDAT pins go to the high impedance state when the MMCIF and the
(DTBUSY_TU)
Input/output pins
CMDSTRT
(DTBUSY)
If the card returns no command response, the command response is detected by the command
timeout error (CTERI).
command response receive end interrupt (CRPI).
detected, the end of the data busy state is then detected through the data busy end interrupt
(DBSYI).
occurs.
MMC card do not drive the bus and the input level of these pins are high because they are
pulled-up internally.
(DBSYI)
(START)
INTSTR0
(CWRE)
MCCMD
(BUSY)
MCCLK
(CMDI)
Figure 24.5 Example of Command Sequence for Commands without Data Transfer
MCDAT
(CRPI)
CSTR
(REQ)
Command transmission period
Command transmission
Command output (48 bits)
started
(No Data Busy State)
Command sequence execution period
Section 24 Multimedia Card Interface (MMCIF)
Rev.1.00 Dec. 13, 2005 Page 905 of 1286
Command response
reception
Response reception
(No busy state)
REJ09B0158-0100
completed

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