R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 636

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
14.3.9
DMARS are 16-bit readable/writable registers that specify the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer request of SCIF0, SCIF1, HAC, HSPI, SIOF, SSI, FLCTL, and MMCIF.
When MID/RID other than the values listed in table 14.4 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits RS[3:0]
has been set to B'1000 for CHCR0 to CHCR5 registers. Otherwise, even if DMARS has been set,
transfer request source is not accepted.
• DMARS0
Rev.1.00 Dec. 13, 2005 Page 584 of 1286
REJ09B0158-0100
Bit
15 to 10
9, 8
7 to 2
1, 0
Initial value:
R/W:
Bit:
DMA Extended Resource Selectors (DMARS0 to DMARS2)
Bit Name
C1MID[5:0] 000000
C1RID[1:0] 00
C0MID[5:0] 000000
C0RID[1:0] 00
R/W
15
0
R/W
14
0
R/W
C1MID[5:0]
13
Initial
Value
0
R/W
12
0
R/W
R/W
R/W
R/W
R/W
R/W
11
0
R/W
10
0
Descriptions
Transfer request module ID5 to ID0 for DMA channel 1
(MID)
See table 14.4.
Transfer request register ID1 and ID0 for DMA channel
1 (RID)
See table 14.4.
Transfer request module ID5 to ID0 for DMA channel 0
(MID)
See table 14.4
Transfer request register ID1 and ID0 for DMA channel
0 (RID)
See table 14.4.
C1RID[1:0]
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
C0MID[5:0]
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
C0RID[1:0]
1
0
R/W
0
0