R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 651

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

• Burst Mode (LCKN = 0, TB = 1)
Figure 14.9 shows DMA transfer timing in burst mode.
DMA Transfer Matrix: Table 14.8 shows the DMA transfer matrix in auto-request mode and
table 14.9 shows the DMA transfer matrix in external request mode, and table 14.10 shows the
peripheral module request.
Table 14.8 DMA Transfer Matrix in Auto-Request Mode (all channels)
[Legend]
Yes:
Note:
Transfer Source
LBSC space
DDRIF space
PCIC space
Peripheral module*
L RAM, SuperHyway RAM Yes
In burst mode, once the DMAC obtains the SuperHyway bus mastership, the transfer is
performed continuously without releasing the bus mastership until the transfer end condition is
satisfied. In external request mode with level detection of the DREQ pin, however, when the
DREQ pin is not active, the bus mastership passes to the other bus master after the DMAC
transfer request that has already been accepted ends, even if the transfer end conditions have
not been satisfied.
Burst mode cannot be used when the peripheral module is the transfer request source.
*
Transfer is available.
DREQ
SuperHyway
bus cycle
When the transfer source or destination is peripheral module register, the transfer size
should be the same value of its access size.
Figure 14.9 DMA Transfer Timing Example in Burst Mode
CPU
LBSC space DDRIF space PCIC space
Yes
Yes
Yes
Yes
CPU
(DREQ Low Level Detection)
CPU
Yes
Yes
Yes
Yes
Yes
DMAC DMAC DMAC
Read
Write
Section 14 Direct Memory Access Controller (DMAC)
Transfer Destination
Read
Yes
Yes
Yes
Yes
Yes
Rev.1.00 Dec. 13, 2005 Page 599 of 1286
DMAC DMAC
Write
Read
Peripheral
module*
Yes
Yes
Yes
Yes
Yes
DMAC
Write
CPU
REJ09B0158-0100
L RAM,
SuperHyway
RAM
Yes
Yes
Yes
Yes
Yes