R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 352

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
interrupt request within this LSI. Processing can be continued without any problem after the
execution of an RTE instruction.
10.4.5
Interrupt Priority Levels of On-chip Module Interrupts
When any interrupt is generated, the INTC outputs the corresponding interrupt exception code
(INTEVT code) to the CPU. The code identifies the individual interrupt source. When the CPU
accepts an interrupt, the corresponding INTEVT code is indicated in INTEVT. Even without
reading the interrupt source register of the INTC, the interrupt source can be identified by reading
INTEVT of the CPU from the interrupt handler. Table 10.12 lists the sources of interrupts and the
corresponding interrupt exception codes.
An on-chip module interrupt source can be assigned any of 30 (5-bit) priority levels (see figure
10.3). The interrupt level-reception interface is four bits wide and thus handles 15 priority levels
(with H'0 as the interrupt-request mask setting). The value in the INTC consists of five bits, one
bit of which is an extension that allows the assignment of an individual priority level to each of the
on-chip modules. When the CPU is notified of the priority, the lowest-order bit is rounded off to
leave four bits of data. For example, two interrupt sources with priority levels set to H'1A and
H'1B will both be output to the CPU as the 4-bit priority level H'D. That is, the two interrupt
sources have the same priority value. However, although the rounded codes are the same for both
interrupt sources, the interrupt with priority level H'1B clearly has priority when we consider the
5-bit data in the priority setting. That is, the 5-bit values in the fields shown in table 10.5 give
INTC a way to differentiate between interrupts with the same four-bit priority level.
Rev.1.00 Dec. 13, 2005 Page 300 of 1286
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