R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 827

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 21.8 shows a sample SCIF initialization flowchart.
in SCSCR (leaving TE, RE, TIE,
Set RTRG1-0, TTRG1-0 bits, and
MCE in SCFCR, and clear TFCL
SCSCR to 1, and set TIE, RIE,
Set TFCL and RFCL bits in
and RIE bits cleared to 0)
Set CKE1 and CKE0 bits
Set data transfer format
Clear TE and RE bits in
1-bit interval elapsed?
Set TE and RE bits in
Set value in SCBRR
Start of initialization
and RFCL bits to 0
End of initialization
Figure 21.8 Sample SCIF Initialization Flowchart
and REIE bits
SCSCR to 0
SCFCR to 1
in SCSMR
Yes
Wait
No
[1]
[2]
[3]
[4]
Section 21 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Wait at least one bit interval, then
set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits.
Setting the TE and RE bits enables
the SCIF_TXD and SCIF_RXD pins
to be used. When transmitting, the
SCIF will go to the mark state;
when receiving, it will go to the idle
state, waiting for a start bit.
Rev.1.00 Dec. 13, 2005 Page 775 of 1286
REJ09B0158-0100