R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 843

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(6)
Figure 21.21 shows a sample flowchart for simultaneous serial data transmission and reception.
Use the following procedure for simultaneous serial transmission and reception after enabling the
SCIF for both transmission and reception.
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode)
Figure 21.21 Sample Simultaneous Serial Transmission and Reception Flowchart
No
No
No
Start of transmission and reception
End of transmission and reception
Write transmit data to SCFTDR,
Read ORER flag in SCLSR
Read TDFE flag in SCFSR
Read RDF flag in SCFSR
SCFRDR, and clear RDF
Clear TE and RE bits
Read receive data in
and clear TDFE flag
flag in SCFSR to 0
All data received?
in SCFSR to 0
in SCSCR to 0
ORER = 1?
TDFE = 1?
RDF = 1?
Yes
No
Yes
Yes
Error handling
[3]
[4]
Section 21 Serial Communication Interface with FIFO (SCIF)
[1]
Yes
[2]
Note:
[1] SCIF status check and transmit data
[2] Receive error handling:
[3] SCIF status check and receive data
[4] Serial transmission and reception
write:
Read SCFSR and check that the
TDFE flag is set to 1, then write
transmit data to SCFTDR, and clear
the TDFE flag to 0. The transition of
the TDFE flag from 0 to 1 can also be
identified by a TXI interrupt.
Read the ORER flag in SCLSR to
identify any error, perform the
appropriate error handling, then clear
the ORER flag to 0.
Transmission/reception cannot be
resumed while the ORER flag is set
to 1.
read:
Read SCFSR and check that RDF =
1, then read the receive data in
SCFRDR, and clear the RDF flag to
0. The transition of the RDF flag from
0 to 1 can also be identified by an
RXI interrupt.
continuation procedure:
To continue serial transmission and
reception, read 1 from the RDF flag
and the receive data in SCFRDR, and
clear the RDF flag to 0 before
receiving the MSB in the current
frame. Similarly, read 1 from the
TDFE flag to confirm that writing is
possible before transmitting the MSB
in the current frame. Then write data
to SCFTDR and clear the TDFE flag
to 0.
When switching from a transmit operation
or receive operation to simultaneous
transmission and reception operations,
clear the TE and RE bits to 0, and then
set them simultaneously to 1.
Rev.1.00 Dec. 13, 2005 Page 791 of 1286
REJ09B0158-0100