R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 905

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
The serial bit clock frequency can be computed using the following formula:
When the HSPI is configured as a slave, the IDIV and CLKC bits are ignored and the HSPI
synchronizes to the externally supplied serial bit clock. The maximum value of the external serial
bit clock that the module can operate with is peripheral clock frequency / 8.
If any of the FBS, CLKP, IDIV or CLKC bit values are changed, then the HSPI will undergo the
HSPI software reset.
Bit
5
4 to 0
Serial bit clock frequency =
Bit Name
IDIV
CLKC4 to
CLKC0
Initial
Value
0
All 0
R/W
R/W
R/W
Initial division ratio
Description
Initial Clock Division Ratio
0: The peripheral clock is divided by a factor of 4
1: The peripheral clock is divided by a factor of 32
Clock Division Count
These bits determine the number of intermediate
frequency cycles long both the high and low periods of
the serial bit clock.
00000: 1 intermediate frequency cycle.
00001: 2 Intermediate frequency cycles.
00010: 3 intermediate frequency cycles.
11111: 32 intermediate frequency cycles.
initially to create an intermediate frequency, which is
further divided to create the serial bit clock when
master mode.
initially to create an intermediate frequency, which is
further divided to create the serial bit clock when
master mode.
:
Peripheral clock frequency
Serial bit clock frequency = Intermediate
frequency / 2.
Serial bit clock frequency = Intermediate
frequency / 4.
Serial bit clock frequency = Intermediate
frequency / 6.
Serial bit clock frequency = Intermediate
frequency / 64.
×
:
Section 23 Serial Protocol Interface (HSPI)
((Clock division count + 1)
Rev.1.00 Dec. 13, 2005 Page 853 of 1286
REJ09B0158-0100
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