R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 936
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 24 Multimedia Card Interface (MMCIF)
• INTSTR2
Rev.1.00 Dec. 13, 2005 Page 884 of 1286
REJ09B0158-0100
Bit
7 to 2
1
0
Bit Name
FRDY_TU
FRDYI
Initial value:
Initial
Value
All 0
Undefined
0
R/W:
Bit:
—
0
R
7
R/W
R
R
R/W
—
R
6
0
Description
Reserved
These bits are always read as 0. The write
value should always be 0.
FIFO Ready Flag
Regardless of set values of DMAEN and
FRDYIE, this bit is read as 0 when FIFO
data amount matches the condition set in
DMACR[2:0], and otherwise, read as 1.
FIFO Ready Interrupt Flag
0: No interrupt
[Clearing condition]
Write 0 after reading FRDYI = 1.
(Writing 1 is invalid)
1: Interrupt requested
[Setting condition]
When remained FIFO data does not match
the assert condition set in DMACR while
DMAEN = 1 and FRDYIE = 1.
Note: FRDYI will be set on the setting
—
R
5
0
condition after clearing. To clear it,
disable the flag setting by FRDYIE
in INTCR2.
—
4
0
R
—
R
3
0
—
2
R
0
FRDY
_TU
—
R
1
FRDYI
R/W
0
0
Interrupt
output
FRDY
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