R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 594

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
In configuration accesses, a PCI master abort (no device connected) will not cause an interrupt.
Configuration writes will end normally. Configuration reads will return a value of 0.
(3)
When the PCIC operates as the host device, a special cycle is generated by setting H'8000 FF00 in
the PCIPAR and writing to the PCIPDR.
(4)
In host bus bridge mode, the PCI bus arbiter in the PCIC is activated.
The PCIC supports four external masters (i.e., four REQ and GNT pairs).
If use of the bus is simultaneously requested by more than one device, the bus is granted to the
device with the highest priority.
The PCI bus arbiter supports two modes to determine the priority of devices: fixed priority and
pseudo-round-robin. The mode is selected by the BMAM bit in PCICR.
Fixed Priority: When the BMAM bit in PCICR is cleared to 0, the priorities of devices are fixed
the following default values.
PCIC > device 0 > device 1 > device 2 > device 3
The PCIC always gains use of the bus over other devices.
Pseudo-Round-Robin: When the BMAM bit in PCICR is set to 1, the most recently granted
device is assigned the lowest priority.
The initial priority is the same as the fixed priority mode.
Rev.1.00 Dec. 13, 2005 Page 542 of 1286
REJ09B0158-0100
Special Cycle Generation
Arbitration
Figure 13.15 Address Generation for Type 0 Configuration Access
Configuration
address register
(PCIPAR)
PCI local bus
address
(AD31 to AD0)
31 30
31
CCIE
Reserved
Only one '1'
24 23
BN
16 15
16 15
00000
DN
11 10
11 10
FN
8 7
8 7
CRA
2 1
2 1
00
00
0
0