R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 848

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 21 Serial Communication Interface with FIFO (SCIF)
Thus, the reception margin in asynchronous mode is given by formula (1).
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L:
F:
From equation (1), if F = 0 and D = 0.5, the reception margin is 46.875%, as given by formula (2).
When D = 0.5 and F = 0:
However, this is a theoretical value. A reasonable margin to allow in system designs is 20% to
30%.
(6)
When using an external clock as the synchronization clock, after SCFTDR is updated by the
DMAC, an external clock should be input after at least five peripheral clock (Pck) cycles. A
malfunction may occur when the transfer clock is input within four cycles after updating SCFTDR
(see figure 21.23).
Rev.1.00 Dec. 13, 2005 Page 796 of 1286
REJ09B0158-0100
Frame length (L = 9 to 12)
Absolute value of clock rate deviation
When Using DMAC to Update SCFTDR in External Clock Synchronizing
M = (0.5 – 1 / (2 × 16) ) × 100% = 46.875% ............................................... (2)
M= (0.5 -
SCIF_SCK
TDFE flag
SCIF_TXD
Note: When the SCIF is operated on an external clock, set t to ensure 5 Pck clock cycles or more.
Figure 21.23 Example of Synchronization Clock Transfer by DMAC
2N
1
) - (L - 0.5) F -
t
D0
D1
| D - 0.5 |
D2
N
D3
(1 + F) × 100 % .................. (1)
D4
D5
D6
D7