R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 235

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

4. When the entry to be replaced in entry replacement is specified by software, write that value to
5. Execute the LDTLB instruction and write the contents of PTEH and PTEL to the UTLB.
6. Finally, execute the exception handling return instruction (RTE), terminate the exception
7.6
To enable the ITLB and UTLB to be managed by software, their contents are allowed to be read
from and written to by a program in the P2 area with a MOV instruction in privileged mode.
Operation is not guaranteed if access is made from a program in another area.
After the memory-mapped TLB has been accessed, execute one of the following three methods
before an access (including an instruction fetch) to an area other than the P2 area is performed.
1. Execute a branch using the RTE instruction. In this case, the branch destination may be an area
2. Execute the ICBI instruction for any address (including non-cacheable area).
3. If the MT bit in IRMCR is 0 (initial value) before accessing the memory-mapped TLB, the
Note that the method 3 may not be guaranteed in the future SuperH Series. Therefore, it is
recommended that the method 1 or 2 should be used for being compatible with the future SuperH
Series.
The ITLB and UTLB are allocated to the P4 area in the virtual address space. VPN, V, and ASID
in the ITLB can be accessed as an address array, PPN, V, SZ, PR, C, and SH as a data array. VPN,
D, V, and ASID in the UTLB can be accessed as an address array, PPN, V, SZ, PR, C, D, WT, and
SH as a data array. V and D can be accessed from both the address array side and the data array
side. Only longword access is possible. Instruction fetches cannot be performed in these areas. For
reserved bits, a write value of 0 should be specified; their read value is undefined.
the URC bits in MMUCR. If URC is greater than URB at this time, the value should be
changed to an appropriate value after issuing an LDTLB instruction.
handling routine, and return control to the normal flow. The RTE instruction should be issued
at least one instruction after the LDTLB instruction.
other than the P2 area.
specific instruction does not need to be executed. However, note that the CPU processing
performance will be lowered because the instruction fetch is performed again for the next
instruction after MMUCR has been updated.
Memory-Mapped TLB Configuration
Section 7 Memory Management Unit (MMU)
Rev.1.00 Dec. 13, 2005 Page 183 of 1286
REJ09B0158-0100