R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 888

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 22 Serial I/O with FIFO (SIOF)
22.4.6
Overview: The transmit and receive FIFOs of the SIOF have the following features.
• 16-stage 32-bit FIFOs for transmission and reception
• The FIFO pointer can be updated in one read or write cycle regardless of access size of the
Transfer Request: The transfer request of the FIFO can be issued to the CPU or DMAC as the
following interrupt sources.
• FIFO transmit request: TDREQ (transmit interrupt source)
• FIFO receive request: RDREQ (receive interrupt source)
The request conditions for FIFO transmit or receive can be specified individually. The request
conditions for the FIFO transmit and receive are specified by the bits TFWM[2:0] and the bits
RFWM[2:0] in SIFCTR, respectively. Table 22.11 and table 22.12 summarize the conditions
specified by SIFCTR.
Table 22.11 Conditions to Issue Transmit Request
Table 22.12 Conditions to Issue Receive Request
Rev.1.00 Dec. 13, 2005 Page 836 of 1286
REJ09B0158-0100
TFWM[2:0]
000
100
101
110
111
RFWM[2:0]
000
100
101
110
111
CPU and DMAC. (One-stage 32-bit FIFO access cannot be divided into multiple accesses.)
FIFO
Number of
Requested Stages
1
4
8
12
16
Number of
Requested Stages
1
4
8
12
16
Receive Request
Valid data is 1 stage or more
Valid data is 4 stages or more
Valid data is 8 stages or more
Valid data is 12 stages or more
Valid data is 16 stages
Transmit Request
Empty area is 16 stages
Empty area is 12 stages or more
Empty area is 8 stages or more
Empty area is 4 stages or more
Empty area is 1 stage or more
Used Areas
Smallest
Largest
Used Areas
Smallest
Largest