R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 662

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 14 Direct Memory Access Controller (DMAC)
The transfer destination is the LBSC space and the DACK is output during the write cycle:
(1) Set B'001 to B'111 (i.e., other than 000) to the IWW bits in CSnBCR
Note: * The transfer source is the LBSC space and the DACK is output during the read cycle or
Table 14.11 to 14.14 shows the register settings that whether or not the negation of the DACK
output with the number of bus cycle generation of the DMA transfer. The DACK is not negated
when the number of the bus cycle that generated in the DMA transfer is 1.
Note that, in the following settings, when either the transfer source or the transfer destination is the
LBSC space, to avoid the DACK is asserted ceaselessly during between the two or more times
DMA transfer, set B'001 to B'111 to the IWRRD, IWRRS or IWW bits in CSnBCR. In this
setting, if the 16-byte DMA transfer is performed, multiple bus cycles are generated and the CSn
is negated between bus cycles, the DREQ signal is not sampled correctly and malfunction may
occur.
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REJ09B0158-0100
the transfer destination is the LBSC space and the DACK is output during the write
cycle. And then specifies no idle cycle (CSnBCR.IWRRD, IWRRS, IWW are cleared
to B'000). Note that the case that both the transfer source and the transfer destination
are the LBSC spaces, does not apply this.