R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 806
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 21 Serial Communication Interface with FIFO (SCIF)
Rev.1.00 Dec. 13, 2005 Page 754 of 1286
REJ09B0158-0100
Bit
4
3
Bit Name
BRK
FER
Initial
Value
0
0
R/W
R/W* Break Detect
R
Description
Indicates that a receive data break signal has been
detected.
0: A break signal has not been received
[Clearing conditions]
•
•
1: A break signal has been received*
[Setting condition]
•
Note: When a break is detected, the receive data
Framing Error
In asynchronous mode, indicates whether or not a
framing error has been found in the data that is to be
read next from SCFRDR.
0: There is no framing error that is to be read from
[Clearing conditions]
•
•
1: There is a framing error that is to be read from
[Setting condition]
•
SCFRDR
SCFRDR
Power-on reset or manual reset
When 0 is written to BRK after reading BRK = 1
When data with a framing error is received, followed
by the space "0" level (low level ) for at least one
frame length
Power-on reset or manual reset
When there is no framing error in the data that is to
be read next from SCFRDR
When there is a framing error in the data that is to
be read next from SCFRDR
(H'00) following detection is not transferred to
SCFRDR. When the break ends and the receive
signal returns to mark "1", receive data transfer is
resumed.
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