R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 348

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
10.4
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip modules. Each interrupt has
a priority level (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set,
the interrupt is masked and interrupt requests are ignored.
10.4.1
The NMI interrupt has the highest priority level of 16. It is always accepted unless the BL bit in
SR of the CPU is set to 1. In sleep mode, the interrupt is accepted even if the BL bit is set to 1.
A setting can also be made to have the NMI interrupt accepted even if the BL bit is set to 1. Input
from the NMI pin is edge-detected. The NMI edge selection bit (NMIE) in ICR0 is used to select
either the rising or falling edge for detection. After modification of the NMIE bit in ICR0, the
NMI interrupt is not detected for at least six bus clock cycles after the modification. When the
INTMU bit in the CPUOPM is set to 1, the interrupt mask level (IMASK) in SR is automatically
modified to level 15 on the acceptance of an NMI interrupt. When the INTMU bit in CPUOPM is
cleared to 0, the IMASK value in SR is not affected by the acceptance of an NMI interrupt.
10.4.2
IRQ interrupts are input by single-pin interrupts on pins IRQ/IRL7 to IRQ/IRL0. IRQ interrupts
are available when pins IRQ/IRL7 to IRQ/IRL0 are made to operate as IRQn (n = 0 to 7)
independent interrupt inputs by setting the IRLM0 and IRLM1 bits in ICR0 to 1.
The IRQnS1 and IRQnS0 bits in ICR1 are used to select one from among rising-edge, falling-
edge, low-level, and high-level detection.
A priority level (from 15 to 0) can be set for each input by writing to INTPRI.
When an IRQ interrupt request is set for detection of the low level or high level, the IRQ interrupt
pin input level should be held until the CPU has accepted the interrupt and started interrupt
exception handling.
When high- or low-level detection has been selected, usage or non-usage of the holding function
for interrupt requests can be selected by setting or clearing the LSH bit in ICR0. When usage of
the holding function has been selected (ICR0.LSH = 0), interrupt requests are held in the detection
circuit and the interrupt request must be cleared in the exception handling routine after acceptance
of the interrupt. For details, refer to section 10.7 Usage Notes. To select non-usage of the holding
function, set the LSH bit in ICR0 to 1. In this case, the operation of IRQ level detection provides
Rev.1.00 Dec. 13, 2005 Page 296 of 1286
REJ09B0158-0100
Interrupt Sources
NMI Interrupt
IRQ Interrupts