R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 910

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 23 Serial Protocol Interface (HSPI)
Rev.1.00 Dec. 13, 2005 Page 858 of 1286
REJ09B0158-0100
Bit
8
7
6
5
4
3
Bit Name
FFEN
LMSB
CSV
CSA
TFIE
ROIE
Initial
Value
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
FIFO Mode Enable
Enables or disables the FIFO mode. When FIFO mode
is enabled two 8-entry deep FIFOs are made available,
one for transmit data and one for receive data. These
FIFOs are read and written via SPTBR and SPRBR.
When FIFO mode is disabled the SPTBR and SPRBR
are used directly so new data must be written to SPTBR
and read from SPRBR for each and every transfer.
FIFO mode must be disabled if DMA requests are also
going to be used to service SPTBR and SPRBR.
0: FIFO mode disabled
1: FIFO mode enabled
LSB/MSB First Control
0: Data is transmitted and received most significant bit
1: Data is transmitted and received least significant bit
Chip Select Value
Controls the value output from the chip select when the
HSPI is a master and the chip select generation has
been selected.
0: Chip select output is low.
1: Chip select output is high.
Automatic/Manual Chip Select
0: Chip select output is automatically generated during
1: Chip select output is manually controlled, with its
Transmit Complete Interrupt Enable
0: Transmit complete interrupt disabled
1: Transmit complete interrupt enabled
Receive Overrun Occurred / Warning Interrupt Enable
0: Receive overrun occurred / warning interrupt
1: Receive overrun occurred / warning interrupt enabled
(MSB) first.
(LSB) first.
data transfer.
value being determined by the CSV bit.
disabled