R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 461
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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32-byte access at address 0
(first round: from address 0)
32-byte access at address 0
(second round: from address 4)
32-byte access at address 0
(third round: from address 8)
32-byte access at address 0
(fourth round: from address 12 (H'C))
32-byte access at address 0
(fifth round: from address 16 (H'10))
32-byte access at address 0
(sixth round: from address 20 (H'14))
32-byte access at address 0
(seventh round: from address 24
(H'18))
32-byte access at address 0
(eighth round: from address 28 (H'1C))
Bit 63
Bit 63
DDR-SDRAM
(Address A + 12)
(Address A + 4)
32 bit
Write
Bit 31
Bit 32 Bit 31
Bit 32 Bit 31
Little endian
(Address A + 12)
(Address A + 0)
(Address A + 4)
(Address A + 8)
Figure 12.3 Data Alignment in DDR-SDRAM and DDRIF
(Address A + 0)
(Address A + 8)
Bit 0
Read
Time
sequence
Bit 0
Bit 0
MD31 to MD24 MD23 to MD16 MD15 to MD8
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Bit 31 to 24
Time
sequence
Example of memory address A[3:0] = 0000
(Other than above: 32-byte wraparound operation)
Bit 63
Bit 63
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
Bit 23 to 16
(Address A + 0)
(Address A + 8)
Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 409 of 1286
Bit 32 Bit 31
Bit 32 Bit 31
Big endian
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
Bit 15 to 8
(Address A + 12)
(Address A + 4)
REJ09B0158-0100
MD7 to MD0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 7 to 0
Bit 0
Bit 0
Time
sequence
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