R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 682

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 16 Watchdog Timer and Reset
16.3.2
WDTCSR is a readable/writable 32-bit register that comprises the timer mode-selecting bit and
overflow flags. Use a longword access to write to the WDTCSR, with H'A5 in the bits 31 to 24.
The reading value of bits 31 to 24 is always H'00.
Rev.1.00 Dec. 13, 2005 Page 630 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 24
23 to 8
7
6
R/W:
R/W:
Bit:
Bit:
Watchdog Timer Control/Status Register (WDTCSR)
Bit Name
(Given
code)

TME
WT/IT
R/W
31
15

R
0
0
R/W
30
14

R
0
0
R/W
29
13

R
0
0
Initial
Value
H'00
All 0
0
0
(Given code)
R/W
28
12

R
0
0
R/W
R/W
R/W
R
R/W
R/W
27
11

R
0
0
R/W
26
10

R
0
0
Description
Reserved (Given code for writing)
These bits are always read as H'00. To write to this
register, the write value must be H'A5.
Reserved
These bits are always read as 0. The write value
should always be 0.
Timer Enable
Specifies starting and stopping of timer operation.
0: Stops counting up
1: Starts counting up
Timer Mode Select
Specifies whether the WDT is used as a watchdog
timer or interval timer. Up counting may not be
performed correctly if this bit is modified while the
WDT is running.
0: Interval timer mode
1: Watchdog timer mode
R/W
25

R
0
9
0
R/W
24

R
0
8
0
R/W
TME
23

R
0
7
0
WT/IT
R/W
22

R
0
6
0
RSTS
R/W
21

R
0
5
0
WOVF
R/W
20

R
0
4
0
IOVF
R/W
19

R
0
3
0
18


R
R
0
2
0
17


R
R
0
1
0
16


R
R
0
0
0