R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 346

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
10.3.15 GPIO Interrupt Set Register (INT2GPIC)
INT2GPIC enables interrupt requests input from the following pins: pins 0 to 6 of port E, pins 0
and 1 of port H, pin 0 of port J, and pins 4 and 5 of port J.
A GPIO interrupt is an active low level-sensed signal. Within the register, bits for the pins are
arranged in four groups. Pins 0 to 2 of port E are allocated to group 0, pins 3 to 5 of port E are
allocated to group 1, pins 0 and 1 of port H, pin 0 of port J, and pin 4 of port K are allocated to
group 2, and pin 5 of port K and pin 6 of port E are allocated to group 3. Before enabling any of
these interrupt requests, set the corresponding pin as an input in the corresponding port-control
register (PECR, PHCR, PJCR, PKCR). For the port-control registers, see section 28, General
Purpose I/O (GPIO).
When a GPIO port pin is configured as an interrupt, the INTC is notified when the interrupt
condition is satisfied on that pin. However, the interrupt is indicated as a one-bit source in the
INT2A0 or INT2A1 register of the INTC. The port and pin on which the interrupt was received
can be identified by referring to the on-chip module interrupt source register INT2B7. The port
group where the interrupt was generated can also be identified by referring to the INTEVT code in
the CPU.
Rev.1.00 Dec. 13, 2005 Page 294 of 1286
REJ09B0158-0100
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
31
15


R
R
0
0
30
14


R
R
0
0
29
13


R
R
0
0
28
12


R
R
0
0
27

11

R
R
0
0
R/W
26
10

R
0
0
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
23


R
R
0
7
0
22


R
R
0
6
0
21


R
R
0
5
0
20


R
R
0
4
0
R/W
19

R
0
3
0
R/W
R/W
18
0
2
0
R/W
R/W
17
0
1
0
R/W
R/W
16
0
0
0