R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 94

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 2 Programming Model
Saved Status Register (SSR) (32 bits, Privileged Mode, Initial Value = Undefined): The
contents of SR are saved to SSR in the event of an exception or interrupt.
Saved Program Counter (SPC) (32 bits, Privileged Mode, Initial Value = Undefined): The
address of an instruction at which an interrupt or exception occurs is saved to SPC.
Global Base Register (GBR) (32 bits, Initial Value = Undefined): GBR is referenced as the
base address of addressing @(disp,GBR) and @(R0,GBR).
Vector Base Register (VBR) (32 bits, Privileged Mode, Initial Value = H'00000000): VBR is
referenced as the branch destination base address in the event of an exception or interrupt. For
details, see section 5, Exception Handling.
Saved General Register 15 (SGR) (32 bits, Privileged Mode, Initial Value = Undefined): The
contents of R15 are saved to SGR in the event of an exception or interrupt.
Debug Base Register (DBR) (32 bits, Privileged Mode, Initial Value = Undefined): When the
user break debugging function is enabled (CBCR.UBDE = 1), DBR is referenced as the branch
destination address of the user break handler instead of VBR.
2.2.5
System Registers
Multiply-and-Accumulate Registers (MACH and MACL) (32 bits, Initial Value =
Undefined): MACH and MACL are used for the added value in a MAC instruction, and to store
the operation result of a MAC or MUL instruction.
Procedure Register (PR) (32 bits, Initial Value = Undefined): The return address is stored in
PR in a subroutine call using a BSR, BSRF, or JSR instruction. PR is referenced by the subroutine
return instruction (RTS).
Program Counter (PC) (32 bits, Initial Value = H'A0000000): PC indicates the address of the
instruction currently being executed.
Rev.1.00 Dec. 13, 2005 Page 42 of 1286
REJ09B0158-0100