R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 598

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 13 PCI Controller (PCIC)
(1)
Figures13.17 is an example of a single-write cycle in host bus bridge mode. Figure 13.18 is an
example of a single read cycle in host bus bridge mode. Figure 13.19 is an example of a burst
write cycle in normal mode. And Figure 13.20 is an example of a burst read cycle in normal mode.
Note that the response speed of DEVSEL and TRDY differs according to the connected target
device. In host bus bridge mode, master accesses always use single read/write cycles. The issuing
of configuration transfers is only possible in host bus bridge mode.
Rev.1.00 Dec. 13, 2005 Page 546 of 1286
REJ09B0158-0100
Master Read/Write Cycle Timing
Figure 13.17 Master Write Cycle in Host Bus Bridge Mode (Single)
[Legend]
Addr:
AP:
Com:
PCICLK
AD[31:0]
PAR
CBE[3:0]
(C/BE[3:0])
PCIFRAME
IRDY
DEVSEL
TRDY
LOCK
IDSEL
REQ
GNT
PCI space address
Address parity
Command
Dn:
DPn:
BEn:
Addr
Com
nth data
nth data parity
nth data byte enable
BE0
AP
D0
DP0