R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 607

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

(3)
By writing 1 to the SC bit in PCICMD, a wait (stepping) of one clock can be inserted when the
PCIC is driving the AD bus. As a result, the PCIC drives the AD bus over 2 clocks. This function
can be used when there is a heavy load on the PCI bus and the AD bus does not achieve the
stipulated logic level in one clock.
When the PCIC operates as the host bus bridge mode, it is recommended to use this function for
the issuance of configuration transfers.
Figure 13.25 is an example of burst memory write cycle with stepping. Figure 13.26 is an example
of target burst read cycle with stepping.
Figure 13.25 Master Write Cycle in Host Bus Bridge Mode (Burst, with stepping)
Address/Data Stepping Timing
PCICLK
AD[31:0]
PAR
CBE[3:0]
(C/BE[3:0])
PCIFRAME
IRDY
DEVSEL
TRDY
[Legend]
Addr:
AP:
Com:
PCI space address
Address parity
Command
Dn:
DPn:
BEn:
Com
Addr
nth data
nth data parity
nth data byte enable
AP
BE0
D0
DP0
BE1
D1
Rev.1.00 Dec. 13, 2005 Page 555 of 1286
DPn-1
Section 13 PCI Controller (PCIC)
BEn
Dn
DPn
REJ09B0158-0100