R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 251
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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• Tag
• V bit (validity bit)
• U bit (dirty bit)
Stores the upper 19 bits of the 29-bit physical address of the data line to be cached. The tag is
not initialized by a power-on or manual reset.
Indicates that valid data is stored in the cache line. When this bit is 1, the cache line data is
valid. The V bit is initialized to 0 by a power-on reset, but retains its value in a manual reset.
The U bit is set to 1 if data is written to the cache line while the cache is being used in copy-
back mode. That is, the U bit indicates a mismatch between the data in the cache line and the
data in external memory. The U bit is never set to 1 while the cache is being used in write-
through mode, unless it is modified by accessing the memory-mapped cache (see section 8.6,
Memory-Mapped Cache Configuration). The U bit is initialized to 0 by a power-on reset, but
retains its value in a manual reset.
Virtual address
22
19
31
MMU
8
Entry selection
255
Figure 8.2 Configuration of Instruction Cache (IC)
0
(way 0 to way 3)
Address array
Comparison
19 bits
Tag
Hit signal
(Way 0 to way 3)
1 bit
V
3
13 12
32 bits
LW0
32 bits
10
LW1
32 bits
LW2
[12:5]
Rev.1.00 Dec. 13, 2005 Page 199 of 1286
(way 0 to way 3)
32 bits
Read data
Data array
LW3
5 4
32 bits
LW4
Longword (LW) selection
2
32 bits
LW5
0
32 bits
LW6
32 bits
Section 8 Caches
REJ09B0158-0100
LW7
LRU
6 bits
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