R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1087

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
21, 20
19
Bit Name
FIFOTRG
[1:0]
AC1CLR
Initial
Value
00
0
R/W
R/W
R/W
Description
FIFO Trigger Setting
Change the condition for the FIFO transfer request.
In flash-memory read:
00: Issue an interrupt to the CPU or a DMA transfer
01: Issue an interrupt to the CPU or a DMA transfer
10: Issue an interrupt to the CPU or a DMA transfer
11: Issue an interrupt to the CPU when FLDTFIFO
In flash-memory programming:
00: Issue an interrupt to the CPU when FLDTFIFO has
01: Issue an interrupt or a DMA transfer request to the
10: Issue an interrupt to the CPU when FLDTFIFO has
11: Issue an interrupt to the CPU when FLDTFIFO has
FLECFIFO Clear
Clears the address counter of FLECFIFO.
0: Retains the address counter value of FLECFIFO. In
1: Clears the address counter of FLECFIFO. After
flash-memory access, this bit should be cleared to 0.
clearing the counter, this bit should be cleared to 0.
request to the DMAC when FLDTFIFO stores 4
bytes of data.
request to the DMAC when FLDTFIFO stores 16
bytes of data.
request to the DMAC when FLDTFIFO stores 128
bytes of data.
stores 128 bytes of data, or issue a DMA transfer
request to the DMAC when FLDTFIFO stores 16
bytes of data.
empty area of 4 bytes or more (do not set DMA
transfer).
CPU when FLDTFIFO has empty area of 16 bytes
or more.
empty area of 128 bytes or more (do not set DMA
transfer).
empty area of 128 bytes or more, or issue a DMA
transfer request to the CPU when FLDTFIFO has
empty area of 16 bytes or more.
Section 27 NAND Flash Memory Controller (FLCTL)
Rev.1.00 Dec. 13, 2005 Page 1035 of 1286
REJ09B0158-0100