R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 362

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 10 Interrupt Controller (INTC)
10.5.2
When multiple interrupts must be handled, the interrupt handling routine should include the
following procedure:
1. Identify the interrupt source by using the INTEVT code as an offset in branching to the
2. Clear the interrupt source in the corresponding interrupt handling routine.
3. Save SSR and SPC on the stack.
4. Clear the BL bit in SR. When the INTMU bit in CPUOPM is set to 1, the interrupt mask level
5. Execute processing as required in response to the interrupt.
6. Set the BL bit in SR to 1.
7. Restore SSR and SPC from the stack.
8. Execute the RTE instruction.
Following this procedure in the above order ensures that, if further interrupts are generated, an
interrupt with higher priority than the one currently being handled can be accepted after step 4.
This reduces the interrupt response time for urgent processing.
10.5.3
Setting the MAI bit in ICR0 to 1 selects masking of interrupts while the NMI signal is low
regardless of the BL and IMASK bit settings in SR.
• Normal operation or sleep mode
All other interrupts are masked while the NMI signal is low. Note that only NMI interrupts due to
NMI signal input are generated.
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REJ09B0158-0100
corresponding interrupt handling routine.
(IMASK) in SR is automatically modified to the priority level of the accepted interrupt. When
the INTMU bit in CPUOPM is cleared to 0, use software to set the IMASK bit in SR to the
same priority level as the accepted interrupt.
Multiple Interrupts
Interrupt Masking by MAI Bit