R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1192

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 30 User Debugging Interface (H-UDI)
30.4
The H-UDI has the following registers.
Table 30.3 Register Configuration (1)
Notes: 1. The P4 address is an address when accessing through P4 area in a virtual address
Table 30.4 Register Configuration (2)
Note:
Table 30.5 Register Status in Each Processing State
Rev.1.00 Dec. 13, 2005 Page 1140 of 1286
REJ09B0158-0100
Register Name
Instruction register
Interrupt source register
Boundary scan register
Bypass register
Register Name
Instruction register
Interrupt source register
Boundary scan register
Bypass register
Register Name
Instruction register
Interrupt source register
2. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
1. The low level of the TRST pin or the Test-Logic-Reset state of the TAP controller
2. When reading via the H-UDI, the value is always H'FFFF FFFD.
3. Only 1 can be written to the LSB by the H-UDI interrupt command.
Register Descriptions
space. The area 7 address is an address when accessing through area 7 in a physical
space using the TLB.
initializes to these values.
initializes to these values.
Abbrev.
SDIR
SDINT
SDBSR
SDBPR
Abbrev.
SDIR
SDINT
SDBSR
SDBPR
Abbrev.
SDIR
SDINT
R/W
R
R/W


R/W
R/W
W*

R/W
Power-On Reset
H'0EFF
H'0000
3
P4 Address*
H'FC11 0000
H'FC11 0018


32
Size
32

1
1
H-UDI Side
H'FFFF FFFD (fixed value*
H'0000 0000
Area 7 Address*
H'1C11 0000
H'1C11 0018


Initial Value*

Undefined
CPU Side
Manual Reset
Retained
Retained
1
1
Size
16
16


Sleep
Retained
Retained
2
)
Initial
Value*
H'0EFF
H'0000


2