R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 102
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 102 of 1342
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Section 2 Programming Model
2.7
2.7.1
This LSI prefetches instructions more drastically than conventional SH-4 to accelerate the
processing speed. Therefore if the instruction in the memory is modified and it is executed
immediately, then the pre-modified code that is prefetched are likely to be executed. In order to
execute the modified code definitely, one of the following sequences should be executed between
the execution of modifying codes and modified codes.
(1)
The target for the ICBI instruction can be any address within the range where no address error
exception occurs.
(2)
The all instruction cache area corresponding to the modified codes should be invalidated by the
ICBI instruction. The ICBI instruction should be issued to each cache line. One cache line is 32
bytes.
(3)
The all operand cache area corresponding to the modified codes should be written back to the
main memory by the OCBP or OCBWB instruction. Then the all instruction cache area
corresponding to the modified codes should be invalidated by the ICBI instruction. The OCBP,
OCBWB and ICBI instruction should be issued to each cache line. One cache line is 32 bytes.
Note: * Processes executed while changing the instructions on the memory dynamically.
Rev.1.00 Dec. 13, 2005 Page 50 of 1286
REJ09B0158-0100
In case the modified codes are in non-cacheable area
In case the modified codes are in cacheable area (write-through)
In case the modified codes are in cacheable area (copy-back)
Usage Note
Notes on self-modified codes*
OCBP @Rm or OCBWB @Rm
SYNCO
ICBI @Rn
SYNCO
ICBI @Rn
SYNCO
ICBI @Rn
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