R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 895

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.4.8
The SIOF has one type of interrupt.
Interrupt Sources: Interrupts can be issued by several sources. Each source is shown as an SIOF
status in SISTR. Table 22.14 lists the SIOF interrupt sources.
Table 22.14 SIOF Interrupt Sources
Whether an interrupt is issued or not as the result of an interrupt source is determined by the SIIER
settings. If an interrupt source is set to 1 and the corresponding bit in SIIER is set to 1, an SIOF
interrupt is issued.
No. Classification
1
2
3
4
5
6
7
8
9
10
11
12
Transmission
Reception
Control
Error
Interrupts
Bit Name
TDREQ
TFEMP
RDREQ
RFFUL
TCRDY
RCRDY
TFUDF
TFOVF
RFOVF
RFUDF
FSERR
SAERR
Function Name
Transmit FIFO transfer
request
Transmit FIFO empty
Receive FIFO transfer
request
Receive FIFO full
Transmit control data
ready
Receive control data
ready
Transmit FIFO
underflow
Transmit FIFO overflow Write to the transmit FIFO is
Receive FIFO overflow Serial data is received while the
Receive FIFO
underflow
FS error
Assign error
Description
The transmit FIFO stores data of
specified size or more.
The transmit FIFO is empty.
The receive FIFO stores data of
specified size or more.
The receive FIFO is full.
The transmit control register is ready
to be written.
The receive control data register
stores valid data.
Serial data transmit timing has arrived
while the transmit FIFO is empty.
performed while the transmit FIFO is
full.
receive FIFO is full.
The receive FIFO is read while the
receive FIFO is empty.
A synchronous signal is input before
the specified bit number has been
passed (in slave mode).
The same slot is specified in both
serial data and control data.
Rev.1.00 Dec. 13, 2005 Page 843 of 1286
Section 22 Serial I/O with FIFO (SIOF)
REJ09B0158-0100