R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 859
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit
9
8
7 to 2
Bit Name
TXE
RXE
—
Initial
Value
0
0
All 0
R/W
R/W
R/W
R
Description
Transmit Enable
0: Disables data transmission from the SIOF_TXD pin
1: Enables data transmission from the SIOF_TXD pin
•
•
This bit is initialized upon a transmit reset.
Receive Enable
0: Disables data reception from SIOF_RXD
1: Enables data reception from SIOF_RXD
•
•
This bit is initialized upon receive reset.
Reserved
These bits are always read as 0. The write value should
always be 0.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF issues a transmit transfer request according to
the setting of the TFWM bit in SIFCTR. When
transmit data is stored in the transmit FIFO,
transmission of data from the SIOF_TXD pin begins.
This bit setting becomes valid at the start of the next
frame (at the rising edge of the SIOF_SYNC signal).
When the 1 setting for this bit becomes valid, the
SIOF begins the reception of data from the
SIOF_RXD pin. When receive data is stored in the
receive FIFO, the SIOF issues a reception transfer
request according to the setting of the RFWM bit in
SIFCTR.
Rev.1.00 Dec. 13, 2005 Page 807 of 1286
Section 22 Serial I/O with FIFO (SIOF)
REJ09B0158-0100
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