R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 687

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 16.2 shows a WDT counting up operation.
16.4.4
WDTBCNT is a 18-bit up-counter operated on the peripheral clock (Pck). WDTBCNT is cleared
when H'55 is set to the bits 31 to 24 in WDTBST.
If the peripheral clock frequency is 50 MHz, the WDTBCNT overflow time is approximately
5.243 ms (= 2^18 [bit]
WDTCNT is a 12-bit counter, starts count up operation when overflow occurs in WDTBCNT. The
time until WDTCNT overflows becomes the maximum value when H'000 are set to WDTST.
Where the peripheral clock frequency is 50 MHz, the maximum overflow time is approximately
21.475 s (= 2^12 [bit]
WDTCNT
value
WDTBCNT
value
WOVF, IOVF
Setting value
of WDTST
H'0003 FFFF
H'0000 0000
H'0000 0000
(internal)
Reset
TME
Time for WDT Overflow
Counting up with
overflow signal of WDTBCNT
Counting up
with Pck
Start counting up
×
×
5.243 [ms]).
1/50 [MHz]).
Figure 16.2 WDT Counting Up Operation
Clear counter
when overflowed
Interval timer mode:
Clear counter when overflowed
Rev.1.00 Dec. 13, 2005 Page 635 of 1286
Section 16 Watchdog Timer and Reset
Set flag
Interval
timer mode
WDT mode:
Clear counter after
reset operation
REJ09B0158-0100
WDT
mode
Time
Time