R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1168
![IC SUPERH MPU ROMLESS 449-BGA](/photos/12/46/124616/r8a77800anbgav_sml.jpg)
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 29 User Break Controller (UBC)
Table 29.3 Settings for Match Data Setting Register
Notes: 1. If the data value is included in the match conditions, be sure to specify the operand
29.2.6
CDMR1 is a readable/writable 32-bit register which specifies the bits to be masked among the
data value bits specified using the match data setting register. (Set the bits to be masked to 1.)
Rev.1.00 Dec. 13, 2005 Page 1116 of 1286
REJ09B0158-0100
Bus and Size Selected
Using CBR1
Operand bus (byte)
Operand bus (word)
Operand bus (longword) SDB31 to SDB24 SDB23 to SDB16 SDB15 to SDB8 SDB7 to SDB0
Bit
31 to 0
Initial value :
Initial value :
R/W:
R/W:
Bit :
Bit :
2. The OCBI instruction is handled as longword write access without the data value, and
3. If the quadword access is specified and the data value is included in the match
Match Data Mask Setting Register 1 (CDMR1)
Bit Name
CDM
size.
the PREF, OCBP, and OCBWB instructions are handled as longword read access
without the data value. Therefore, do not include the data value in the match conditions
for these instructions.
conditions, the upper and lower 32 bits of 64-bit data are each compared with the
contents of both the match data setting register and match data mask setting register.
R/W
R/W
31
15
R/W
R/W
30
14
Initial
Value
Undefined
R/W
R/W
29
13
CD[31:24]
Don't care
Don't care
R/W
R/W
28
12
R/W
R/W
27
11
R/W
R/W
R/W
R/W
26
10
Description
Compare Data Value Mask
Specifies the bits to be masked among the data value
bits specified using the CDR1 register. (Set the bits to
be masked to 1.)
0: Data value bits CD[n] are included in the break
1: Data value bits CD[n] are masked and not included
[n] = any values from 31 to 0
CD[23:16]
Don't care
Don't care
R/W
R/W
25
9
condition.
in the break condition.
R/W
R/W
24
8
CDM
CDM
R/W
R/W
23
7
R/W
R/W
22
6
CD[15:8]
Don't care
SDB15 to SDB8 SDB7 to SDB0
R/W
R/W
21
5
R/W
R/W
20
4
R/W
R/W
19
3
CD[7:0]
SDB7 to SDB0
R/W
R/W
18
2
R/W
R/W
17
1
R/W
R/W
16
0
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