R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 40

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Figure 24.18 Example of Command Sequence for Commands with Write Data
Figure 24.19 Example of Operational Flow for Commands with Write Data
Figure 24.20 Example of Operational Flow for Commands with Write Data (1)
Figure 24.20 Example of Operational Flow for Commands with Write Data (2)
Figure 24.20 Example of Operational Flow for Commands with Write Data (3)
Figure 24.20 Example of Operational Flow for Commands with Write Data (4)
Figure 24.21 Example of Operational Flow for Commands with Write Data
Figure 24.22 Example of Read Sequence Flow (Single Block Transfer) ................................... 934
Figure 24.23 Example of Read Sequence Flow (1) (Open-ended Multiple Block Transfer)...... 935
Figure 24.23 Example of Read Sequence Flow (2) (Open-ended Multiple Block Transfer)...... 936
Figure 24.23 Example of Read Sequence Flow (3) (Pre-defined Multiple Block Transfer) ...... 937
Figure 24.23 Example of Read Sequence Flow (4) (Pre-defined Multiple Block Transfer) ...... 938
Figure 24.24 Example of Operational Flow for Stream Read Transfer ...................................... 939
Figure 24.25 Example of Operational Flow for Auto-mode
Figure 24.25 Example of Operational Flow for Auto-mode
Figure 24.26 Example of Write Sequence Flow (1) (Single Block Transfer)............................. 944
Figure 24.26 Example of Write Sequence Flow (2) (Single Block Transfer)............................. 945
Figure 24.27 Example of Write Sequence Flow (1) (Open-ended Multiple Block Transfer)..... 946
Figure 24.27 Example of Write Sequence Flow (2) (Open-ended Multiple Block Transfer)..... 947
Figure 24.27 Example of Write Sequence Flow (3) (Pre-defined Multiple Block Transfer)...... 948
Figure 24.27 Example of Write Sequence Flow (4) (Pre-defined Multiple Block Transfer)...... 949
Figure 24.28 Example of Operational Flow for Stream Write Transfer ..................................... 950
Figure 24.29 Example of Operational Flow for Auto-mode
Figure 24.29 Example of Operational Flow for Auto-mode
Section 25 Audio Codec Interface (HAC)
Figure 25.1 Block Diagram ........................................................................................................ 956
Figure 25.2 AC97 Frame Slot Structure ..................................................................................... 973
Figure 25.3 Initialization Sequence ............................................................................................ 976
Figure 25.4 Sample Flowchart for Off-Chip Codec Register Write ........................................... 977
Rev.1.00 Dec. 13, 2005 Page xxxviii of l
(Stream Transfer)................................................................................................... 924
(Single Block Transfer) ......................................................................................... 925
Pre-defined Multiple Block Read Transfer (2) ...................................................... 941
(Open-ended Multiple Block Transfer) ................................................................. 926
(Open-ended Multiple Block Transfer) ................................................................. 927
(Pre-defined Multiple Block Transfer).................................................................. 928
(Pre-defined Multiple Block Transfer).................................................................. 929
(Stream Transfer) .................................................................................................. 930
Pre-defined Multiple Block Read Transfer (1)...................................................... 940
Pre-defined Multiple Block Write Transfer (1)..................................................... 951
Pre-defined Multiple Block Write Transfer (2)..................................................... 952