R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 263

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

8.3.4
In order to give priority to data reads to the cache and improve performance, this LSI has a write-
back buffer which holds the relevant cache entry when it becomes necessary to purge a dirty cache
entry into external memory as the result of a cache miss. The write-back buffer contains one cache
line of data and the physical address of the purge destination.
8.3.5
This LSI has a 64-bit buffer for holding write data when writing data in write-through mode or
writing to a non-cacheable area. This allows the CPU to proceed to the next operation as soon as
the write to the write-through buffer is completed, without waiting for completion of the write to
external memory.
8.3.6
When the OC2W bit in RAMCR is set to 1, OC two-way mode which only uses way 0 and way 1
in the OC is entered. Thus, power consumption can be reduced. In this mode, only way 0 and way
1 are used even if a memory-mapped OC access is made.
The OC2W bit should be modified by a program in the P2 area. At that time, if the valid line has
already been recorded in the OC, data should be written back by software, if necessary, 1 should
be written to the OCI bit in CCR, and all entries in the OC should be invalid before modifying the
OC2W bit.
Write-Back Buffer
Write-Through Buffer
OC Two-Way Mode
Physical address bits [28:5]
Figure 8.4 Configuration of Write-Through Buffer
Figure 8.3 Configuration of Write-Back Buffer
Physical address bits [28:0]
LW0
LW1
LW2
LW3
LW0
Rev.1.00 Dec. 13, 2005 Page 211 of 1286
LW4
LW1
LW5
LW6
LW7
Section 8 Caches
REJ09B0158-0100