R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 409
R8A77800ANBGAV
Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet
1.R8A77800ANBGV.pdf
(1342 pages)
Specifications of R8A77800ANBGAV
Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 409 of 1342
- Download datasheet (7Mb)
11.5.2
(1)
For area 0, physical address bits 28 to 26 are 000.
The interfaces that can be set for this area are the SRAM, burst ROM and MPX interfaces.
A bus width of 8, 16, or 32 bits is selectable with external pins MODE4 and MODE3 at a power-
on reset. For details, see section 11.3.2, Memory Bus Width.
When area 0 is accessed, the CS0 signal is asserted.
In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write
control signals WE0 to WE3 are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted by CS0WCR can be selected.
When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable
with bits BW2 to BW0 in CS0BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
When the burst ROM interface is used, the number of transfer cycles for a burst cycle is selected
from a range of 2 to 9 according to the number of wait cycles.
The setup time and hold time (cycle number) of the address and CS0 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS0WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more.
(2)
For area 1, physical address bits 28 to 26 are 001.
The interfaces that can be set for this area are the SRAM, burst ROM, MPX and byte-control
SRAM interfaces.
A bus width of 8, 16, or 32 bits is selectable with bits SZ in CS1BCR. When the MPX interface is
used, a bus width of 32 bits should be selected through bits SZ in CS1BCR. When using the byte-
control SRAM interface, select a bus width of 16 or 32 bits.
When area 1 is accessed, the CS1 signal is asserted.
Area 0
Area 1
Areas
Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 357 of 1286
REJ09B0158-0100
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