R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 456

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 12 DDR-SDRAM Interface (DDRIF)
12.3
12.3.1
This LSI supports both 29-bit and 32-bit physical address spaces (29-bit address mode and 32-bit
address extended mode), and the address space is selectable from among five kinds of map by
setting Memory Address Map Select Register (MMSELR) of the LBSC. Figure 12.2 shows the
physical address space of this LSI.
The DDRIF supports both 29-bit and 32-bit physical address spaces and can control an externally
connected DDR-SDRAM memory space with up to 256 Mbytes.
The setting in MMSELR for the 29-bit address mode gives the DDRIF control of not only area 3,
but also areas 2, 4, and 5, which are also within the 29-bit address range. The DDRIF can control a
total of 4 areas with a maximum capacity of 256 Mbytes as the external DDR-SDRAM memory
space.
In the case of the 32-bit address extended mode, the DDRIF controls not only area 3 (and, with
some settings, area 2, 4 and 5) within the 29-bit address range but also DDR-SDRAM areas in the
physical address range from H'4000 0000 to H'7FFF FFFF. However, this 1-Gbyte range includes
areas where the areas actually allocated to the DDRIF by the MMSELR are shadowed. The actual
area controlled by the DDRIF as the external DDR-SDRAM memory space is still a total of 256
Mbytes.
For further information on the 32-bit address extended mode, see section 7.7, 32-Bit Address
Extended Mode.
Rev.1.00 Dec. 13, 2005 Page 404 of 1286
REJ09B0158-0100
Address Space, Bus Width, and Data Alignment
Address Space of the DDRIF