R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 410

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 11 Local Bus State Controller (LBSC)
In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write
control signals WE0 to WE3 are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted by CS1WCR can be selected.
When the burst ROM interface is used, a burst pitch number in the range of 0 to 7 is selectable
with bits BW2 to BW0 in CS1BCR.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS1 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS1WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more.
(3)
Area 2
For area 2, physical address bits 28 to 26 are 010.
The interfaces that can be set for this area are the SRAM, burst ROM, MPX and DDR-SDRAM
interfaces.
When the SRAM interface is used, a bus width of 8, 16, or 32 bits is selectable with bits SZ in
CS2BCR. When the MPX interface is used, a bus width of 32 bits should be selected through bits
SZ in CS2BCR.
When area 2 is accessed, the CS2 signal is asserted (except for DDR-SDRAM area).
In the case where the SRAM interface is set, the RD signal, which can be used as OE, and write
control signals WE0 to WE3 are asserted.
For the number of bus cycles, 0 to 25 wait cycles inserted by CS2WCR can be selected.
Any number of wait cycles can be inserted in each bus cycle through the external wait pin (RDY).
(When the insert number is 0, the RDY signal is ignored.)
The setup time and hold time (cycle number) of the address and CS2 signals to the read and write
strobe signals can be set within a range of 0 to 7 cycles by CS2WCR. The BS hold cycles can be
set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more.
When using area 2 for the DDR-SDRAM interface, set the AREASEL bit in MMSELR. Then the
CS2 signal is not asserted. When the DDR-SDRAM is used, see section 12, DDR-SDRAM
Interface (DDRIF).
Rev.1.00 Dec. 13, 2005 Page 358 of 1286
REJ09B0158-0100