R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 698

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 17 Power-Down Mode
17.3.1
MSTPCR is a 32-bit readable/writable register that can individually start or stop the module
assigned to each bit.
MSTPCR can be accessed only in longwords.
Rev.1.00 Dec. 13, 2005 Page 646 of 1286
REJ09B0158-0100
Initial value:
Initial value:
Bit
31 to 22
21
20 to 14
R/W:
R/W:
Bit:
Bit:
Standby Control Register (MSTPCR)
Bit Name

MSTP21

31
15


R
R
0
0
30
14


R
R
0
0
MSTP13 MSTP12 MSTP11 MSTP10 MSTP9
R/W
29
13

R
0
0
Initial
Value
All 0
0
All 0
R/W
28
12

R
0
0
R/W
27

11
R
0
0
R/W
R
R/W
R
R/W
26
10

R
0
0
R/W
25

Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Module Stop Bit 21
To make a transition to the DMAC module standby
mode, confirm that the DME bits in DMA operation
registers (DMAOR0 and DMAOR1) are cleared to 0
or all TE bits in DMA channel control registers
(CHCRn, n = 0 to 11) are set to 1.
0: Supplies the clock to the DMAC module
1: Stops the clock supply to the DMAC module
Reserved
These bits are is always read as 0. The write value
should always be 0.
R
0
0
9
MSTP8
R/W
24

R
0
8
0
23


R
R
0
7
0
22


R
R
0
6
0
MSTP21
MSTP5
R/W
R/W
21
0
5
0
MSTP4
R/W
20

R
0
4
0
MSTP3
R/W
19

R
0
3
0
MSTP2
R/W
18

R
0
2
0
MSTP1
R/W
17

R
0
1
0
MSTP0
R/W
16

R
0
0
0