R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 1089

IC SUPERH MPU ROMLESS 449-BGA

R8A77800ANBGAV

Manufacturer Part Number
R8A77800ANBGAV
Description
IC SUPERH MPU ROMLESS 449-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77800ANBGAV

Core Processor
SH-4A
Core Size
32-Bit
Speed
400MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
75
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.15 V ~ 1.35 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
449-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77800ANBGAV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Bit
7
6
5
4
Bit Name
BTOERB
TRREQF1 0
TRREQF0 0
STERINTE 0
Initial
Value
0
R/W
R/W
R/W
R/W
R/W
Description
Timeout Error
This bit is set to 1 if a timeout error occurs (the bits
RBTIMCNT[19:0] in FLBSYCNT are decremented to 0).
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no timeout error occurs
1: Indicates that a timeout error occurs
FLECFIFO Transfer Request Flag
Indicates that a transfer request is issued from
FLECFIFO.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no transfer request is issued from
1: Indicates that a transfer request is issued from
FLDTFIFO Transfer Request Flag
Indicates that a transfer request is issued from
FLDTFIFO.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no transfer request is issued from
1: Indicates that a transfer request is issued from
Interrupt Enable at Status Error
Enables or disables an interrupt request to the CPU
when a status error has occurred.
0: Disables the interrupt request to the CPU by a status
1: Enables the interrupt request to the CPU by a status
error
error
FLECFIFO
FLECFIFO
FLDTFIFO
FLDTFIFO
Section 27 NAND Flash Memory Controller (FLCTL)
Rev.1.00 Dec. 13, 2005 Page 1037 of 1286
REJ09B0158-0100

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