R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 395

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bit
27
26 to 24 ADH
23
22 to 20 RDS
Bit Name


Initial
Value
0
111
0
111
R/W
R
R/W
R
R/W
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Address Hold Cycle
Specify the number of cycles to be inserted to ensure
the address hold time to the CSn negation. (Available
only when the SRAM interface, byte control SRAM
interface, or burst ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Reserved
This bit is always read as 0. The write value should
always be 0.
RD Setup Cycle (CSn Assertion–RD Assertion Delay
Cycle)
Specify the number of cycles to be inserted form CSn
assertion to RD assertion (Available only when the
SRAM interface, byte control SRAM interface, or burst
ROM interface is selected.)
000: No cycle inserted
001: 1 cycle inserted
010: 2 cycles inserted
011: 3 cycles inserted
100: 4 cycles inserted
101: 5 cycles inserted
110: 6 cycles inserted
111: 7 cycles inserted
Section 11 Local Bus State Controller (LBSC)
Rev.1.00 Dec. 13, 2005 Page 343 of 1286
REJ09B0158-0100