R8A77800ANBGAV Renesas Electronics America, R8A77800ANBGAV Datasheet - Page 913

• Manufacturer Part Number: R8A77800ANBGAV
• Description: IC SUPERH MPU ROMLESS 449-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77800ANBGAV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 75
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.15 V ~ 1.35 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 449-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

23.4
23.4.1
Figure 23.2 shows the flow of a transmit/receive operation procedure.
Depending on the settings of SPCR, the master transmits data to the slave on either the falling or
rising edge of HSPI_CLK and samples data from the slave on the opposite edge. The data transfer
between the master and slave completes when the transmit complete status flag (TXFN) in SPSR
is set to 1. This flag should be used to identify when an HSPI transfer event (byte transmitted and
byte received) has occurred, even in the case where the HSPI module is being used to receive data
only (null data being transmitted). By default data is transmitted MSB first, but LSB first is also
possible depending on how the LMSB bit in SPSCR is set.
Operation
Operation Overview without DMA (FIFO Mode Disabled)
Yes
operation by setting the MASL bit
setting TFIE and ROIE bits in
Select required interrupts by
Select master or slave
Write data to SPTBR
TXBUFF is empty by
reading the TXFL bit
transmit required?
Reset the system
Figure 23.2 Operational Flowchart
in SPSCR
in SPSR
Check if
Another
SPSCR
Start
End
No
Yes
No
Section 23 Serial Protocol Interface (HSPI)
Rev.1.00 Dec. 13, 2005 Page 861 of 1286
TX/RX data to/from slave
REJ09B0158-0100